1. Field of the Invention
The present disclosure relates to the field of computer processors, and, in particular, to a processor comprising a first and a second mode of operation.
2. Description of the Related Art
In modern computer systems, processors are employed which comprise a plurality of instructions. The processor reads instructions and data from a system memory connected to the processor and modifies the instructions and/or data in accordance with the instructions. The system memory may comprise volatile but quickly accessible memory devices, such as RAMs, as well as slow but permanent memory devices, such as hard disks. Moreover, the computer may receive input from devices such as a keyboard, a mouse and/or a network connection and may provide output to devices such as a monitor, one or more loudspeakers and/or a printer. In most computer systems, a specialized computer program, which is denoted as an “operating system,” is employed to control the processing of various programs as well as the transfer of data between the components of the computer system.
FIG. 1a shows a schematic block diagram of a computer system 100 according to the state of the art. The computer system 100 comprises a processor 101, a system memory 107 and one or more input/output devices 108. Arrows 106 schematically indicate the transfer of data between the processor 101, the system memory 107 and the input/output device(s) 107.
The processor 101 comprises a plurality of registers 102, 103, 104, 105. Data may be read from the system memory 107 into the registers 102-105, and data in the registers 102-105 may be written to the system memory 107. The processor 101 may comprise instructions adapted to modify the contents of the registers 102-105, as well as instructions to transfer data between the registers 102-105 and the system memory 107 and/or between the registers 102-105. Moreover, instructions which perform a combination of such tasks may be provided. Typically, the processor 101 may access data in the registers 102-105 much faster than data stored in the system memory 107.
Therefore, in order to increase the performance of the computer system 100, it may be desirable to increase the number of registers of the processor 101. In particular, media processing, including 3D graphics, can benefit significantly from a greater number of registers.
In computer systems according to the state of the art, however, an increase of the number of registers or any other additional state of the processor 101 may require a modification of the operating system, as will be explained in the following with reference to FIG. 1b. 
FIG. 1b shows a schematic flow diagram of a task 201 running on the processor 101 in the computer system 100 according to the state of the art. The task 201 comprises a plurality of instructions 210-215 which are to be processed sequentially by the processor 101. Hence, the processor 101 proceeds from instruction 210 to instruction 211 and from instruction 211 to instruction 212.
While the task 201 is processed, for example, during or after the processing of instruction 212, an interrupt or exception may occur, which is indicated schematically by arrow 230 in FIG. 1b. An exception may be generated in case of an error during the processing of instruction 212, for example, in case of a division by zero or in case of an error message from the system memory 107, such as a page fault. Exceptions may also be generated regularly by instructions of the task 201, for example by instruction 212. A typical application of an exception generated by the task 201 is a call of the operating system of the computer system 100. Interrupts may be generated by events originating from devices other than the processor 101, for example, by input into the input/output device 108, or by a synchronization request of the input/output device 108. If multitasking is performed in the computer system 100, interrupts generated by a timing circuit may be employed to alternately activate the various tasks, which may be processes or threads.
In case of an interrupt or exception, the execution of the task 201 may be interrupted and an interrupt routine 202, which may, for example, be part of the operating system, is executed. The interrupt routine 202 comprises a plurality of instructions 220-225. These instructions are processed sequentially. After processing the last instruction 225 of the interrupt routine 202, processing of the task 201 is continued at the instruction following the instruction 212 at which the interrupt occurred, i.e., in the above example, at instruction 213.
The interrupt routine 202 may modify the content of the registers 102-105 of the processor 101. In order to insure that the task 201 will function properly in spite of the interrupt or exception, after the occurrence of the interrupt or exception, the content of the registers 102-105 is copied to a storage location in the system memory 107. Before the execution of the task 201 is continued, the content of the storage location is read back into the registers 102-105. Thus, when the execution of the task 201 is continued by executing the instruction 213, the registers 102-105 may comprise substantially the same data as if the instruction 213 would have been executed immediately after instruction 212.
In computer systems 100 according to the state of the art, copying of the content of the register to the storage location and back is effected by instructions provided in the interrupt routine 202, which are implemented as part of the operating system of the computer system 100. Hence, in case additional registers are provided in the processor 101, modifications of the operating system may be required to insure that, in the event of an interrupt or exception, the content of all registers is correctly stored in the system memory and read back into the registers after the completion of the interrupt routine. If a manufacturer of computer processors creates a new processor providing extended features compared to its predecessor, such features, when using additional processor states, i.e., additional registers, may not be reasonably used until manufacturers of operating systems implement support for the added features.
It is, therefore, an object of the present disclosure to provide a computer processor having a second mode of operation wherein the second mode of operation may be used without there being a need for modifications of an operating system providing support only for a first mode of operation of the processor.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.